1. Field of the Invention
The present invention relates to testing a memory and more particularly to an address generator of a built-in self test circuit for testing a memory such as a dynamic random access memory (DRAM) and an address generating method thereof.
2. Description of the Related Art
A built-in self test (BIST) circuit can typically be used as part of a memory testing circuit to test a memory. In a DRAM BIST, the memory to be tested is a DRAM. An address generator in such a BIST circuit is used to generate addresses of the memory to access memory locations to be tested and therefore typically performs many up and down counting operations according to the method being used to test the memory. In the case of an address generator which uses an up/down counter, the size of the circuitry becomes an important consideration since such counters can be very large. Accordingly, it is hard to optimize the area of such devices.
In the case of testing a DRAM which does not use all its available addresses, if the addresses are generated using an up/down counter, various additional circuits are necessary to accomodate the skipping of addresses. This additional circuitry adds to the difficulty in optimizing the area of the BIST circuit including the address generator. Also, in the case that the DRAM does not use all the available addresses, if the address generator is designed using the up/down counter or separate up and down counters, respective counters for counting the column address and the row address of the DRAM are produced. This also greatly increases circuit size and complexity. Also, the hardware of the BIST controlling portion for controlling the up/down counter or the up and down counters can be very large and complex .
It is a first object of the present invention to provide an address generator of a dynamic memory testing circuit, for generating addresses for testing a dynamic memory which uses all the available addresses.
It is a second object of the present invention to provide an address generator of a dynamic memory testing circuit, for generating addresses for testing a dynamic memory which does not use some of the addresses of the memory, and more particularly, a dynamic memory which does not use its most significant addresses among all the available addresses.
It is a third object of the present invention to provide an address generator of a dynamic memory testing circuit, for generating addresses for testing a dynamic memory which does not use some of the middle addresses among all the available addresses.
It is a fourth object of the present invention to provide an address generating method of a dynamic memory testing circuit, for generating addresses for testing a dynamic memory which uses all its available addresses.
It is a fifth object of the present invention to provide an address generating method of a dynamic memory testing circuit, for generating addresses for testing a dynamic memory which does not use some of the addresses of the memory, and more particularly, a dynamic memory which does not use its most significant addresses among all the available addresses.
It is a sixth object of the present invention to provide an address generating method of a dynamic memory testing circuit, simply generating addresses for testing a dynamic memory which does not use some of the middle addresses among all the available addresses.
To achieve these and other objects, there is provided an address generator of a dynamic memory testing circuit for testing the dynamic memory which uses all the available addresses, comprising an N-bit binary up counter where N is the total of the number of memory row address bits and the number of column address bits, an inverting means, and a first selecting means. The N-bit binary up counter performs an up counting operation and outputs the counted value of N bits as an address used by the dynamic memory. The inverting means inverts the counted value of N bits and outputs the inverted value. The first selecting means selectively outputs either the output of the inverting means or the counted values of N bits to the dynamic memory, depending on the state of a select signal generated corresponding to a step of the process of testing the dynamic memory.
In accordance with another aspect of the invention, there is provided an address generator of a dynamic memory testing circuit for testing a dynamic memory which does not use some of the most significant addresses among all the available addresses, comprising an N-bit binary up counter where N is the total of the number of memory row address bits and the number of column address bits, a subtracting means, and a first selecting means. The N-bit binary up counter performs an up counting and outputs the counted value of N bits as an address used by the dynamic memory. The subtracting means subtracts the counted value of N bits from the maximum address and outputs the subtracted value of N bits. The first selecting means selectively outputs either the subtracted value of N bits or the counted values of N bits to the dynamic memory depending on the state of a select signal generated corresponding to a step of the process of testing the dynamic memory.
In accordance with another aspect of the invention, there is provided an address generator of a dynamic memory testing circuit for testing the dynamic memory which does not use some of the middle addresses among all the available addresses, comprising an N-bit binary up counter where N is the total of the number of memory row address bits and the number of column address bits, an inverting means, a subtracting means, a bit combining means, and a first selecting means. The N-bit binary up counter performs an up counting operation and outputs the counted value of N bits as an address used by the dynamic memory. The inverting means inverts the most significant bit (MSB) portion of the counted value of N bits and outputs the inverted value. The subtracting means subtracts the least significant bit (LSB) portion among the counted values of N bits from the LSB portion of the maximum address used in the dynamic memory and outputs the result. The bit combining means combines the output of the inverting means with the output of the subtracting means. The first selecting means selectively outputs to the dynamic memory either the output of the bit combining means or the counted values of N bits, depending on the state of a first select signal generated corresponding to a step of the process of testing the dynamic memory.
In accordance with another aspect of the invention, there is provided a method for generating addresses of a dynamic memory testing circuit for testing a dynamic memory which uses all the available addresses, comprising the steps of (a) obtaining addresses of N bits used by the dynamic memory by performing an up counting operation, the number N being the total of the number of memory row address bits and the number of column address bits, (b) inverting the counted N-bit address, (c) determining whether the dynamic memory is to be tested by increasing or decreasing addresses, (d) generating the N-bit address as addresses for testing the dynamic memory in the case of testing the dynamic memory by increasing the addresses, and (e) generating inverted N-bit addresses as addresses for testing the dynamic memory in the case of testing the dynamic memory by decreasing the addresses.
In accordance with another aspect of the invention, there is provided a method for generating addresses of a dynamic memory testing circuit for testing the dynamic memory which does not use some of most significant addresses among all the available addresses, comprising the steps of (a) obtaining N-bit addresses used by the dynamic memory by performing an up counting operation, the number N being the total of the number of memory row address bits and the number of column address bits, (b) subtracting the N-bit address from the maximum address, and (c) determining whether the dynamic memory is to be tested by increasing or decreasing the addresses, (d) generating the N-bit addresses for testing the dynamic memory when the dynamic memory is to be tested by increasing the addresses, and (e) generating the subtracted result as an address for testing the dynamic memory when the dynamic memory is to be tested by decreasing the addresses.
In accordance with another aspect of the invention, there is provided a method for generating addresses of a dynamic memory testing circuit for testing the dynamic memory which does not use some of the middle addresses among all the available addresses, comprising the steps of (a) obtaining the N-bit addresses used by the dynamic memory by performing an up counting operation, the number N being the total of the number of memory row address bits and the number of column address bits, (b) inverting the MSB portion in the N-bit address, (c) subtracting the LSB portion of the N-bit address from the LSB portion of the maximum address used by the dynamic memory, (d) combining the inverted result with the subtracted result, (e) determining whether the dynamic memory is to be tested by increasing or decreasing the addresses, (f) generating the N-bit address as an address for testing the dynamic memory in the case of testing the dynamic memory by increasing the addresses, and (g) generating the combined result as an address for testing the dynamic memory in the case of testing the dynamic memory by decreasing the addresses.
In each of these aspects of the invention, a down counter can be used instead of an up counter. In either case, the address generating apparatus and method of the invention provide memory testing addresses in either an ascending or descending order, depending on the status of control signals used to set the mode of operation as desired.
The invention can operate to generate testing addresses in the desired order and using only the selected portions of addresses using only a single counter, either an up counter or a down counter. Because only a single counter is used, significant savings in counter circuit size and complexity can be realized. In addition, because only a single counter can be used, the associated controlling circuitry is also smaller and less complex and, therefore, less costly to develop and manufacture.